Assuming for the moment that there is more than one
size of inverter and more than one application for an
inverting CMOS stage, the answer is obvious - know what
you want to achieve, and make it so.
Do you care about delay symmetry? layout area? Drive
strength and symmetry or deliberate asymmetry of that?
Asymmetric inverters from a common signal source are
a good way to make a nonoverlap clock. Alternate Hl
and lH inverters on one side, hL and Lh on the other, as
many times as it takes to reliably open the gap.