Newbie level 6
I am trying to design a basic circuit block of inverter (Analog circuit) in Cadence Virtuoso schematic in 22nm technology. It will be used for non-overlapping clock generator. I need to size the P-MOS and N-MOS. To choose a preliminary size, I can do parametric simulation of varying W with minimum L in DC analysis and transient analysis for desired delay. What figure of merit should I look into to choose the size? Should I look into DC analysis simulation where the graph (VTC) cuts the middle of input clock voltage for falling edge? Or is there any other way through simulation to decide for the sizes except going to the layout phase which comes later after full circuit simulation?