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Figure of Merit for sizing P-MOS and N-MOS in Inverter circuit

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Newbie level 6
Jun 30, 2017
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I am trying to design a basic circuit block of inverter (Analog circuit) in Cadence Virtuoso schematic in 22nm technology. It will be used for non-overlapping clock generator. I need to size the P-MOS and N-MOS. To choose a preliminary size, I can do parametric simulation of varying W with minimum L in DC analysis and transient analysis for desired delay. What figure of merit should I look into to choose the size? Should I look into DC analysis simulation where the graph (VTC) cuts the middle of input clock voltage for falling edge? Or is there any other way through simulation to decide for the sizes except going to the layout phase which comes later after full circuit simulation?

Mostly in technologies below 28nm, pmos and nmos are of similar strength. In that case, you can go with equal sizes for both. You can determine the inverter trip point either in DC or transient sim if you are interested. Based on that you can size pmos/nmos ratio to hit a precise vdd/2 trip point. Concerned about noise, then you should see what inverter size drives what size (i.e fan out) to keep the total noise including jitter amplification minimum.
Assuming for the moment that there is more than one
size of inverter and more than one application for an
inverting CMOS stage, the answer is obvious - know what
you want to achieve, and make it so.

Do you care about delay symmetry? layout area? Drive
strength and symmetry or deliberate asymmetry of that?

Asymmetric inverters from a common signal source are
a good way to make a nonoverlap clock. Alternate Hl
and lH inverters on one side, hL and Lh on the other, as
many times as it takes to reliably open the gap.

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