It really depends on 1, the clock frequency different between the wrclk and rdclk, 2, package size ( meaningful data length between idles).
There are two extreme scenarios
1, with clock frequency difference to be infinity big ( one clock with f=0, and the other one is f=infinity), then no matter how big the fifo is, the fifo will filled up immediately
2, with clock frequency difference to be zero, (same clock frequency, i know we are talking about async case now), we just need a fifo with depth of 1 to absorb the phase difference
However, the package size should be considerate in the case that there are finite frequency difference between to two clocks. And the fifo size matters when data transfer from fast clock domain to slow clock domain. fifo should be big enough to swallow all the data coming from the fast clock domain before the slow clock domain take them out. there will be idle deleting on the slow clock domain. therefore, the fifo size is related to the package size, i.e., how many entries before the fifo see the next idle...
Hope this answer your question.
How to calculate the FIFO depth of a FIFO when we use the FIFO to transfer data from one clock domain to another? Is there any minimum depth that is required?