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How to calculate the FIFO depth of a FIFO when we use the FIFO to transfer data from one clock domain to another? Is there any minimum depth that is required?
This link which I saw earlier does not contain a detail description and contain only a limited information. I raised the post for more descriptive, detail information.
I am aware of the above link for past five years. I am looking for something more than what is described there. In the above link only for a particular burst scenario has been solved.
If anybody has working knowledge more into async FIFO design please reply.
It really depends on 1, the clock frequency different between the wrclk and rdclk, 2, package size ( meaningful data length between idles).
There are two extreme scenarios
1， with clock frequency difference to be infinity big ( one clock with f=0, and the other one is f=infinity), then no matter how big the fifo is, the fifo will filled up immediately
2, with clock frequency difference to be zero, (same clock frequency, i know we are talking about async case now), we just need a fifo with depth of 1 to absorb the phase difference
However, the package size should be considerate in the case that there are finite frequency difference between to two clocks. And the fifo size matters when data transfer from fast clock domain to slow clock domain. fifo should be big enough to swallow all the data coming from the fast clock domain before the slow clock domain take them out. there will be idle deleting on the slow clock domain. therefore, the fifo size is related to the package size, i.e., how many entries before the fifo see the next idle...
How to calculate the FIFO depth of a FIFO when we use the FIFO to transfer data from one clock domain to another? Is there any minimum depth that is required?
However, the package size should be considerate in the case that there are finite frequency difference between to two clocks. And the fifo size matters when data transfer from fast clock domain to slow clock domain. fifo should be big enough to swallow all the data coming from the fast clock domain before the slow clock domain take them out. there will be idle deleting on the slow clock domain. therefore, the fifo size is related to the package size, i.e., how many entries before the fifo see the next idle...
Your point number 1 and point number 2 is good. But your last but one passage that is quoted above describes the depth calculation in general and at a top view. I am looking for mor elaboratie description in detail and also if possible include some examples please.
As mentioned by sun_ray, the general FIFO depth calculation is described many places.
But the minimum depth for async FIFO is little tricky.
The trick here is, the synchronization part of full/empty signals across rd and wr clk domains.
Take the case of FIFO depth = 2 or 4 and draw the waveforms for FIFO full/empty conditions assertion and de-assertion. Once FIFO is full, it stalls the wr side more than the required time as there will be delay in de-asserting the full condition notification to wr side.
You can notice that the same is eliminated when the FIFO depth is 8. The min FIFO depth for Async FIFO is 8.
Can you please answer of my following question
How to calculate the FIFO depth of a FIFO when we use the FIFO to transfer data from one clock domain to another?
I am looking for a detailed and more elaborate answer.
Can you please answer of my following question
How to calculate the FIFO depth of a FIFO when we use the FIFO to transfer data from one clock domain to another?
I am looking for a detailed and more elaborate answer.
Can you please answer of my following question
How to calculate the FIFO depth of a FIFO when we use the FIFO to transfer data from one clock domain to another?
I am looking for a detailed and more elaborate answer.
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