FIFO Depth Calculation

[vipulsinha]

Hi Guys

What could be the optimal buffer for an asynchronous FIFO with the source clock

at 50 MHz and the Read clock is 25 MHz


Data is clming as 8 bits with each clock write . There is no idle cycle. We have to keep the synchronization latancy also into account.


Thanks

Vips

 

[asicengineer1]

If there is no idle cycle in write, and writes keep happening, and ur read is happening at 1/2 the frequency of write, then ur fifo depth can only be infinite.

 

[haneet]

hey Vipul,

I found this link which speaks about hte FIFO depth computation

https://www.asic-world.com/tidbits/fifo_depth.html

regards

Haneet