May 4, 2010 #1 V vipulsinha Member level 2 Joined Nov 9, 2005 Messages 44 Helped 4 Reputation 8 Reaction score 0 Trophy points 1,286 Activity points 1,661 Hi Guys What could be the optimal buffer for an asynchronous FIFO with the source clock at 50 MHz and the Read clock is 25 MHz Data is clming as 8 bits with each clock write . There is no idle cycle. We have to keep the synchronization latancy also into account. Thanks Vips
Hi Guys What could be the optimal buffer for an asynchronous FIFO with the source clock at 50 MHz and the Read clock is 25 MHz Data is clming as 8 bits with each clock write . There is no idle cycle. We have to keep the synchronization latancy also into account. Thanks Vips
May 4, 2010 #2 A asicengineer1 Member level 2 Joined Jan 16, 2007 Messages 47 Helped 4 Reputation 8 Reaction score 2 Trophy points 1,288 Activity points 1,595 If there is no idle cycle in write, and writes keep happening, and ur read is happening at 1/2 the frequency of write, then ur fifo depth can only be infinite.
If there is no idle cycle in write, and writes keep happening, and ur read is happening at 1/2 the frequency of write, then ur fifo depth can only be infinite.
May 17, 2010 #3 H haneet Full Member level 3 Joined Nov 7, 2006 Messages 160 Helped 14 Reputation 28 Reaction score 1 Trophy points 1,298 Activity points 2,219 hey Vipul, I found this link which speaks about hte FIFO depth computation https://www.asic-world.com/tidbits/fifo_depth.html regards Haneet
hey Vipul, I found this link which speaks about hte FIFO depth computation https://www.asic-world.com/tidbits/fifo_depth.html regards Haneet