FIFO DEPTH and BURST SIZE!

[xman24]

Hi

I am not understanding the word BURST ?! and the Burst size....

then problem is like this ..

FIFO width is 1 bit.

Write Clock freq=50MHz
It will write into 8 locations in FIFO at 50Mhz.

Read Clock=25MHz
It will read 32 locations in FIFO at 20 MHz.


There no latency in between.

Pls help..
Not able to use equations and all. amy be I am not aware of this burst concept.

Thanks

 

[xman24]

pls help regarding the above question.

 

[eeeraghu]

Hi considering the burst of above i/p & o/p requirements and assuming each ip data freq is at 50 MHz (i.e total 8 * 20ns = 160 ns) then for a best case the depth wud be 8 & for worst case depth wud be 32. This is my understanding only.

 

[xman24]

Hi considering the burst of above i/p & o/p requirements and assuming each ip data freq is at 50 MHz (i.e total 8 * 20ns = 160 ns) then for a best case the depth wud be 8 & for worst case depth wud be 32. This is my understanding only.

how did you take the best case and worst case!??? please explain...and if you know about burst,pls explain about that....

 

[eeeraghu]

best case/good case = write data is always ready whenever the fifo's full is 0, worst case = write data writing on its required time.
Burst is sequence of data as given in ur requirement 8 locations so 8 different data's in sequence back to back. i.e 1st-> 2nd -> ....... 8th also said as 8 beat burst i.e 8 data's back to back.