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Few checklist for PLD,FPGA design

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jay_ec_engg

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HI friends.
I found few checklist/guidelins for FPGA/CPLD design. I am not able to understand few. Please help me understanding them

(1) Have all NAND-gates whose fanouts exceed four been buffered ?
(2) Have AND-OR-INVERT elements been used where fanout is low ?
(3)Are test lines available to override feedback loops beteen flip-flops?
(4) Have glitch sources been avoided on all control signals?

I am not able to understand what exactly I have to check for this ?
 

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