Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Few checklist for PLD,FPGA design

Status
Not open for further replies.

jay_ec_engg

Full Member level 3
Joined
Jun 19, 2004
Messages
155
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Location
India
Activity points
1,581
HI friends.
I found few checklist/guidelins for FPGA/CPLD design. I am not able to understand few. Please help me understanding them

(1) Have all NAND-gates whose fanouts exceed four been buffered ?
(2) Have AND-OR-INVERT elements been used where fanout is low ?
(3)Are test lines available to override feedback loops beteen flip-flops?
(4) Have glitch sources been avoided on all control signals?

I am not able to understand what exactly I have to check for this ?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top