[SOLVED] extra commands for VCS simulator

[niladri.s.debnath]

Hello everybody
I am a student working on a project. I am trying to simulate a DAA filter which has critical path delay of 6.4 ns but when i am doing prelayout simulation using back annotation (with .sdf file) by giving clock period less than 6ns still i am able to get the output. Can anybody tell me how it is happening , and if there is any option or switch command which can help me to find that whether setup time violation is taking place or not.

 

[ic_qiand]

Hi niladri.s.debnath!

R u sure ur critical path is not a false path?

To my knowledge, we dont need any particular cmd for setup time check.

VCS will do it automatically if the sdf is annotated correctlly.

 

[niladri.s.debnath]

Hi ic_qiand,
Thanks for the reply
I don't think it will be a false path because its just an adder tree, definitely there will be one input that will activate the path. But suppose such input is given which activates the path, whether it will be able to latch the data although it will be wrong ? or it will display any error msg or anything else ? And also in case of setup time violation where to check for it ?

 

[ic_qiand]

Hi niladri.s.debnath!

It is definitely true that VCS will check setup time and hold time if SDF is annotated and "-notimingcheck" is not used.I've glanced the VCS cmds this morning.

I'm sure, basically, Suppose some violations exist, VCS will give out a waring about them. such as violation types, which path, when it comes out, and whats more signals related to violations will turn to X.

Actually, I didn't try to sim a project with a clk whose period is less than a critical path, course I thought it could give no more than a red "X" or many "X"s.

As for ur design, I think u may check the critical path, where is it, since it is not that complex. Can it be the impossible path?

best regards!

 

[niladri.s.debnath]

hi ic_qiand
thanks for ur reply .....
i was able to solve the problem.....