niladri.s.debnath
Newbie level 6
Hello everybody
I am a student working on a project. I am trying to simulate a DAA filter which has critical path delay of 6.4 ns but when i am doing prelayout simulation using back annotation (with .sdf file) by giving clock period less than 6ns still i am able to get the output. Can anybody tell me how it is happening , and if there is any option or switch command which can help me to find that whether setup time violation is taking place or not.
I am a student working on a project. I am trying to simulate a DAA filter which has critical path delay of 6.4 ns but when i am doing prelayout simulation using back annotation (with .sdf file) by giving clock period less than 6ns still i am able to get the output. Can anybody tell me how it is happening , and if there is any option or switch command which can help me to find that whether setup time violation is taking place or not.