cafukarfoo
Full Member level 3
Hello Sir/Madam,
I run a design both in 400KHz and 1.1MHz clock constraint.
For design constraint in 400kHz,
total leakage power = 2.7uW
For design constraint in 1.1MHz,
total leakage power = 0.7 uW
Can anyone help to explain this? THanks.
I run a design both in 400KHz and 1.1MHz clock constraint.
For design constraint in 400kHz,
total leakage power = 2.7uW
For design constraint in 1.1MHz,
total leakage power = 0.7 uW
Can anyone help to explain this? THanks.