Jul 20, 2010 #1 A alangs Member level 3 Joined Feb 5, 2010 Messages 57 Helped 3 Reputation 6 Reaction score 3 Trophy points 1,288 Location india Activity points 1,681 how it will be assigned reg1<= #10 reg2 ; reg3 = # 10 reg4 ;
Jul 20, 2010 #2 A amraldo Advanced Member level 4 Joined Aug 29, 2004 Messages 1,183 Helped 145 Reputation 290 Reaction score 37 Trophy points 1,328 Location Egypt Activity points 5,880 Re: Plz explain this There are assignemnt. One will be assigned at the end of the always block the other will be assigned after the delay insterted #10. -- Amr
Re: Plz explain this There are assignemnt. One will be assigned at the end of the always block the other will be assigned after the delay insterted #10. -- Amr
Jul 20, 2010 #3 R rca Advanced Member level 5 Joined May 20, 2010 Messages 1,527 Helped 355 Reputation 710 Reaction score 336 Trophy points 1,363 Location Marin Activity points 8,773 Plz explain this the delay # is related the timescale, generaly define at the start of the verilog file, or define by the simulator
Plz explain this the delay # is related the timescale, generaly define at the start of the verilog file, or define by the simulator
Jul 20, 2010 #4 C ckaa Junior Member level 3 Joined Apr 6, 2006 Messages 31 Helped 6 Reputation 12 Reaction score 0 Trophy points 1,286 Activity points 1,476 Re: Plz explain this You have an intra-assignment delay for a blocking and non-blocking statement. You should be able to figure this one out after going through this pdf - www.sutherland-hdl.com/.../1996CUG-presentation_nonblocking_assigns.pdf
Re: Plz explain this You have an intra-assignment delay for a blocking and non-blocking statement. You should be able to figure this one out after going through this pdf - www.sutherland-hdl.com/.../1996CUG-presentation_nonblocking_assigns.pdf