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Explain me how would this be assigned

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alangs

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how it will be assigned
reg1<= #10 reg2 ;
reg3 = # 10 reg4 ;
 

Re: Plz explain this

There are assignemnt. One will be assigned at the end of the always block the other will be assigned after the delay insterted #10.
--
Amr
 

Plz explain this

the delay # is related the timescale, generaly define at the start of the verilog file, or define by the simulator
 

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