Expertise in ASIC Synthesis

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Hello Friends,

At this time I have a question for skill sets.

I have worked on DC synthesis - Full chip upto certain extent. have idea about design contraints, scan insertion, timings; along with that I have resolved some of the real issues which were present in DC netlist.

But my question is - How do I say that I know Full chip synthesis, what are the factors which I should be aware of?

I know there are number of members who have expertise in ASIC Full chip Synthesis, -
So along with them requesting All to comment on it.

Thank you.
 

Need your inputs... - Thanks..
 

For Full chip Synthesis :
-> How do we stitch the lower level blocks in Top level synthesis
-> How to achieve better QoR with bottom up approach
-> What type constraints needed in Full chip synthesis compared to module level synthesis
-> How do u control the synthesis Runs times for larger designs.
-> How u manage the constraints for different blocks and how often do u update them
-> How do u deliver the full chip netlist to PD team n equivalence check team
-> What are the automation techniques used for full chip synthesis compared to block level synthesis

many more...
 

Thanks Sam!!

Would like to hear that - many more...

But before that I will work on the points which you mentioned - though I have idea for few of those...

But of-course will illustrate those points & upgrade my knowledge..
 

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