Event simulation result question?

[xiongdh]

///////////////////////////////////////////////////////
style1:
reg reg_temp1,reg_temp2;
initial
begin
reg_temp1<=1'b0;
reg_temp2<=1'b0;
end
always @(posedge clock)
reg_temp1<=!reg_temp1;

always @(posedge clock & reg_temp1)
reg_temp2<=!reg_temp2;
//////////////////////////////////////////////////////


///////////////////////////////////////////////////////
style2:
reg reg_temp1,reg_temp2;
initial
begin
reg_temp1<=1'b0;
reg_temp2<=1'b0;
end
always @(posedge clock)
reg_temp1<=!reg_temp1;

always @(posedge clock )
if(reg_temp1)
reg_temp2<=!reg_temp2;
//////////////////////////////////////////////////////
with simulation tool verilog-xl
the simulation result is not the same. with style 1.the wave of two signal is the same. with style 2 reg_temp1 's frequence is two times of reg_temp2.
Why this happen????????????

 

[khorram]

That is all right. Please trace the following cases:

In the style1:
The first always causes the "reg_temp1" toggles when the "clock" rises. The second always senses rising of the reg_temp1 and clock. Because the assignment to the reg_temp1 performs in the delta time, so the always condition will be true at that time the reg_temp1 rised. in other words, the rising of a signal can be detected as the same time of modifying. But the value of that signal can not.

In the style2:
The first always causes the "reg_temp1" toggles when the "clock" rises. But the second always just sense rising of the clock and check the value of the reg_temp1. New value of the reg_temp1 is not valid in rising of clock and the previous value of the reg_temp1 will be considered.

Regards,
KH