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ESD protection principle

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mengcy

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For some reason I have to adopt the structure below to provide the ESD path from vdd to vss.however, I don't know how to choose the value for R and C. If the size of the NMOS changes, how does it influence the ESD ability?
 

dick_freebird

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File does not appear to be a real .jpg, not viewable.

In a dynamic clamp you are in a box:

Sensitivity / trigger time must catch the zap before it exceeds
damage threshold. This is probably where scaling comes in,
though you might be better off with active drive than raw
C value.

RC decay time must persist until the source energy has been
dissipated. Too early a release may apply residual source
energy to the part, without the leading-edge dV/dt needed to
retrigger.

A backstop DC trigger is a good idea if you have one that is
low enough voltage, and consistent enough, to be useful.

Suppressing trigger with a vdd-controlled shunt can help you
deal with high speed waveforms (not-trigger on normal
operating dV/dt).
 

shrad

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hi

you should consider evaluating this device: https://www.lasorb.com/

designed for laser diodes, but the bluray version has higher voltage (between 5V and 8V) so it might fit

it is nice enough to protect a laser diode from a static zap, so it should give protection to other circuits as well
 

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