ESD protection diodes/SCR layout

DN+ will raise the junction breakdown and force some other region into play. Such as channel reach-through or allow some better controlled trigger. Could also be that if unprotected that drain would become the current- crowding point of failure at over-the-top ESD levels.

Question whether this is truly a SCR or just a GGNMOS snapback clamp, the turning and turnoff are way different.
For SCRrs you need to take care about the turnoff, you want a GTOSCR that will absolutely turn off under all valid powered application conditions. If a logic level input can keep a SCR lit then you have an angry customer problem.

Device design has a huge impact on gate-turnoff ability and this is the province of old-timey tricks and in-fab cut-and-try (been there, got the patent).

Thanks. I don't believe it is a GGNMOS, there are no poly gates anywhere near ESD protection. That N well also extends under the bond pad itself, but not quite all the way. Would not it just form a large area nwell to substrate diode? Here is what it looks like, both p+ fingers and p+ guard ring connect to ground.