ESD in Bump pad options.

[bsrin]

Hi Everyone,
I worked on ESD layouts in Wirebond option IP where VDD/VSS is connected to internal circuit through ESD cell.
Now , I am working on Bump option IP. My doubt is whether I need to connect the VDD/VSS bump to the IP power mesh through ESD circuit which is 400um wide from esd circuit. With this, VDD to ESD and to IP power mesh will be huge which again creates an IR Drop issue.

Can somebody suggest me how they have connected the bump VDD/VSS to Internal PowerSupply Mesh.
Can we connect bump VDD/VSS(bump placement is nearly middle of IP) to Internal power mesh directly which also connects to ESD block which is sitting bottom of the IP.

Thanks in Advance,
bsrin

 

[D.A.(Tony)Stewart]

A series R (15k for example) is expected to limit the power handling characteristics of the diode which is inverse to its ESR ~1/W and often CMOS is rated for 5mA to 10mA max. Thus also the power dissipation in the series R and diode drop for dissipating the Joules discharged from the standard human hand model.

I recall cascaded R-CR circuits are used to each rail.

There is more to this, but that's off the top of my head.

 

[bsrin]

Hi Sunny,
Yes, R-creates the Joule heating. I have 0.44ohm on vss to clamp and 0.5 on vdd to clamp on Z layer. So, total 0.94 ohm from vdd to vss pad which I guess satisfies ESD rule (<1ohm).
1) Does this 800um (pad to pad) current path can tolerate with esd current?
2) Can we connect Bump pad sitting on IP to Internal Power mesh directly.
Below is the picture which illustrates bump placement (blue color), esd clamp placement(yellow color), Internal power mesh (Green, light Green color).



Can anybody share your experience.

Thanks in Advance.
bsrin

 

[dick_freebird]

Your ESD current is presumed to be a one-time deal and so
the interconnect survivability current density requirement is
less stringent than your advertised-life-at-worst-case-
environment DC current density. I've used 1E6 A/cm2 as
a Jmax for single pulsed current events of uS-range duration
and have never seen an open circuit failure. Your I*R concern
may or may not matter depending on how the threat voltage
is dropped, relative to the victim terminal points inside the
part. If the drops are outboard of both, no prob. If the clamp
is degrade in hold-down ability and the victim is pad-pad,
then you've got a subpar clamp. Try drawing out the whole
current loop (for various entry/exit pad pair combos) and
note resistances and drops along the route, at your ESD
model*voltage of interest. You may find it more tolerable
to upsize clamp width in one spot (esp. if under a pad or
some other non-valued real estate) than making all of the
bussing so fat that you get an arbitrarily low resistance.

 

[D.A.(Tony)Stewart]

Hi Sunny,
Yes, R-creates the Joule heating. I have 0.44ohm on vss to clamp and 0.5 on vdd to clamp on Z layer. So, total 0.94 ohm from vdd to vss pad which I guess satisfies ESD rule (<1ohm).
1) Does this 800um (pad to pad) current path can tolerate with esd current?
2) Can we connect Bump pad sitting on IP to Internal Power mesh directly.
Below is the picture which illustrates bump placement (blue color), esd clamp placement(yellow color), Internal power mesh (Green, light Green color).


View attachment 119408
Can anybody share your experience.

Thanks in Advance.
bsrin

The limiting factor is the ESR on the Schottky diode which as in all diodes is about 10R if 1/10W but this impedance ratio determines the V rise. So compute this with your input series resistor (~15K) so 1 Ohm is ok. But you may need to cascade 2 diode ccts and then check rise time effects with Ciss.