ERROR:Xst:827 Signal Tag_write_s cannot be synthesized, bad synchronous description.

[Tapojyoti Mandal]

--This is a single process design of the FSM
Process(clk,rst)
begin
			--Initialization of signals
			state_s<=idle;
			Tag_we_s<='0';
			Dataram_we_s<='0';
			Tag_write_s<="XX";
			Valid_write_s<='X';
			Dirty_write_s<='X';
			Dataram_input_sel_s<='X';
			Mem_we_out<='0';
			Mem_Addr_out<="XXXXXXXX";
			cpu_ready_out<='0';													
			Mem_valid_out<='0';

	IF rst='1' THEN
		state_s<=idle;
		cpu_ready_out<='1';
	ELSIF clk'EVENT and clk='1' THEN
		CASE state_s IS
			WHEN idle=>
				IF Cpu_valid_in='1' THEN
					state_s<=compare_tag;
					cpu_ready_out<='0';
				ELSE
					state_s<=state_s;
					cpu_ready_out<='1';
				END IF;
				
			WHEN compare_tag =>
				IF Hit_s='1' THEN
					IF Cpu_we_in='0' THEN
						state_s<=idle;												
						cpu_ready_out<='1';											
					ELSIF Cpu_we_in='1' THEN
						state_s<=nothing;
						Tag_we_s<='1';
						Dataram_we_s<='1';
						Tag_write_s<=Tag_read_s;									
						Valid_write_s<='1';											
						Dirty_write_s<='1';											
						Dataram_input_sel_s<='0';									
						cpu_ready_out<='0';											
					END IF;

				ELSIF (Hit_s='0') THEN
					IF Dirty_read_s='0' THEN										
						IF (Valid_read_s='0' and Cpu_we_in='1') THEN
							state_s<=nothing;
							Tag_we_s<='1';											
							Dataram_we_s<='1';										
							Tag_write_s<=Cpu_addr_in(7 downto 6);														
							Valid_write_s<='1';										
							Dirty_write_s<='1';										
							Dataram_input_sel_s<='0';
							cpu_ready_out<='0';
						ELSE
							state_s<=allocate;
							Tag_we_s<='1';											
							Dataram_we_s<='0';										
							Tag_write_s<=Cpu_addr_in(7 downto 6);													
							Valid_write_s<='1';										
							Dirty_write_s<=Cpu_we_in;								
							--memory request from main mermory
							Mem_valid_out<='1';
							cpu_ready_out<='0';
							Mem_we_out<='0';
							Mem_Addr_out<=Cpu_addr_in;								 
						END IF;
					
					ELSIF (Dirty_read_s='1') THEN									
						state_s<=write_back;
						Tag_we_s<='1';												
						Dataram_we_s<='0';											
						Tag_write_s<=Cpu_addr_in(7 downto 6);															
						Valid_write_s<='1';											
						Dirty_write_s<=Cpu_we_in;									
						Dataram_input_sel_s<='X';
						--memory request from main mermory
						Mem_valid_out<='1';
						cpu_ready_out<='0';
						Mem_Addr_out<=Tag_read_s & Cpu_addr_in(5 downto 0);			
						Mem_we_out<='1';
					END IF;
				END IF;

			WHEN allocate =>
					cpu_ready_out<='0';
				IF(Mem_ready_in='1') THEN 										
					state_s<=compare_tag;
					Dataram_we_s<='1';											
					Dataram_input_sel_s<='1';
					Mem_we_out<='0';											
					Mem_Addr_out<=Cpu_addr_in;
					Mem_valid_out<='0';											
				ELSE
					state_s<=state_s;												
					Mem_we_out<='0';											
					Mem_Addr_out<=Cpu_addr_in;
					Mem_valid_out<='1';
				END IF;
				
			WHEN write_back =>
					cpu_ready_out<='0';
				IF (Mem_ready_in='1') THEN
					state_s<=allocate;
					Mem_we_out<='0';											
					Mem_Addr_out<=Cpu_addr_in;									
					Mem_valid_out<='1';											
				ELSE
					state_s<=state_s;
					Mem_we_out<='1';											
					Mem_Addr_out<=Tag_read_s & Cpu_addr_in(5 downto 0);			
					Mem_valid_out<='1';
				END IF;
				
			WHEN nothing =>
				state_s<=idle;
				cpu_ready_out<='1';						
		END CASE;
	END IF;
END Process;

I have checked other posts who had similar query but there the problem was that they were not strictly following the syntax recommended for synchronous design. I am trying to design a FSM using a single Process syntax as provided in Xilinx XST guide and i am strictly following the syntax provided in guide.
I have reviewed the code multiple times and I hope I have not made any syntactical errors, yet I am getting this error.
Is the use of multiple If-else inside the CASE causing the error? But in XST guide also they have used similar code.

 

[ads-ee]

You can't initialize a signal to X. There is no such thing as X in hardware. You are also missing the default clause (which is where you should assign X)

 

[Tapojyoti Mandal]

You can't initialize a signal to X. There is no such thing as X in hardware. You are also missing the default clause (which is where you should assign X)

Should I intialize with something other than 'X' such as '0' or '1' as per the requirement of my FSM.
And I couldn't understand what you meant by 'default clause'.I mean from forums i have learnt that one should always initialize the signals before using them in a FSM process. Is 'default clause' any particular syntax of initializing? Where can I refer it for more information(for example any guide like the XST guide).

 

[ads-ee]

default is what VHDL uses as a keyword in a case statement as the default output when the current state can't be matched (e.g. state variable goes U, X, Z, or to an undefined state value).

Sorry the default clause uses others (I write almost exclusively in Verilog).
https://www.ics.uci.edu/~jmoorkan/vhdlref/cases.html

 

[Tapojyoti Mandal]

default is what VHDL uses as a keyword in a case statement as the default output when the current state can't be matched (e.g. state variable goes U, X, Z, or to an undefined state value).

Sorry the default clause uses others (I write almost exclusively in Verilog).
http://www.ics.uci.edu/~jmoorkan/vhdlref/cases.html

Thankyou, for pointing towards not including the default case in my code.But i would like to bring into light something relevant to this.
Before this Process, i had designed this same FSM using the three process style mentioned in Xilinx XST guide where we use 3 different processes to define our FSM.
proc1: To define the change in state. It has (clk,rst) as the sensitivity list.
proc2: To define the next_state. It has the present_state and the various inputs that i am checking in the case statements as my sensitivity list.
proc3: to define the output based on present state.

The thing is that I had used the syntax as provided in XST guide and used the same CASE statements without the default case(which is obviously a mistake) but still when i simulated it it gave the correct results. This means that not having a default case was not the cause of this error.
I am speculating that maybe the error has to do with the various signals that I am using in my If-Else conditions within the case statements. But I have strictly followed the syntax provided in guide and also there is no syntax error.
I have also ensured that I have not committed this specific mistake: http://www.xilinx.com/support/answers/14047.html

 

[FvM]

No signal that is assigned under the clock edge event (= is synthesized as registered) can be assigned in a different path.

In so far all "Initialization of signals" statements are misplaced. They must go into the reset or the clockedge code.

 

[TrickyDicky]

You can't initialize a signal to X. There is no such thing as X in hardware. You are also missing the default clause (which is where you should assign X)

You can. And there shouldnt be a problem. The synthesisor will probably just ignore them and change them so either '0' or '1' however it sees fit.
The problem is actually because signals are assigned values outside of the clock/reset branches.

 

[ads-ee]

Tricky, I'm always learning something about VHDL from you, FvM, std_match, etc...I'd be the first to admit my VHDL is very rusty. I actually used it for about 10 years then switched to Verilog. I suppose I dislike being told by the language that this is a number and this is a bit-vector and you can't just use either whenever you want. As a purely hardware type (I designed digital processing boards using SSI parts) to me wires/connections are just that, how you interpret the data should be left up to the engineer and Verilog allows that. VHDL forces me to be more like a software engineer and put everything in a "type" container and that makes my brain hurt ;-).

 

[Tapojyoti Mandal]

You can. And there shouldnt be a problem. The synthesisor will probably just ignore them and change them so either '0' or '1' however it sees fit.
The problem is actually because signals are assigned values outside of the clock/reset branches.

Yes, after i removed the initialization and explicitly assigned all the signals in each and every branch of if-else conditions the error was removed.
But I have used this methodology of initialization in a 3 process syntax of defining FSM as provided in XST guide. I think in single process style the sensitivity list includes (clk,rst) and it doesn't allows initialization of signals. While in 3 process style initialization of signals is allowed in process 2(it was not giving any errors).

I would like to ask one more question. What if I have around 20-30 signals that are to be assigned in the FSM and in every if-else conditional branch I need to take care of only 3-4 signals. In that case I would have to explicitly assign all the 20-30 signals even though I really care about the required 3-4 signals. Is there any solution to this cumbersome task of assigning each and every signal or it has to be done the hard way?

 

[FvM]

But I have used this methodology of initialization in a 3 process syntax of defining FSM as provided in XST guide. I think in single process style the sensitivity list includes (clk,rst) and it doesn't allows initialization of signals. While in 3 process style initialization of signals is allowed in process 2(it was not giving any errors).

I reckon a misunderstanding. What we see in the post #1 code isn't a signal initialization. An initialization would be performed in Verilog with an initial block and in VHDL in the signal declaration. It's assigning defined values to all signals once during power-on-reset.

- - - Updated - - -

I reviewed a recent XST user guide (v 14.5) and the only correlation I can find is the "FSM with Three Always Blocks Verilog Coding Example". I don't see how a three process VHDL structure could make sense.

 

[TrickyDicky]

Yes, after i removed the initialization and explicitly assigned all the signals in each and every branch of if-else conditions the error was removed.
But I have used this methodology of initialization in a 3 process syntax of defining FSM as provided in XST guide. I think in single process style the sensitivity list includes (clk,rst) and it doesn't allows initialization of signals. While in 3 process style initialization of signals is allowed in process 2(it was not giving any errors).

I would like to ask one more question. What if I have around 20-30 signals that are to be assigned in the FSM and in every if-else conditional branch I need to take care of only 3-4 signals. In that case I would have to explicitly assign all the 20-30 signals even though I really care about the required 3-4 signals. Is there any solution to this cumbersome task of assigning each and every signal or it has to be done the hard way?

I think you're getting confused between synchronous and asynchronous processes.

In an asynchronous process, defining defaults in the way you describe (putting an assignment before any if/case statments) is the recommended way of coding, to minimise the assignments.

But in a synchronous process, all assignments must be inside the reset/clk branches only. Defaults can be assigned, as above, but are placed inside the clock branch before any control statements, which then get overridden in specific states.