Error when compiling Xilinx IP in QuestaSim

[paulgiro]

Hello,

I have a project in Vivado 2014.4 and am simulating in QuestaSim 10.3c. When I go to simulate, I get the following error when compiling in QuestaSim:

# ** Error: ...../blank_delay_32x7ram/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vh_rfs.vhd(46): Can't recompile existing unprotected design unit "dist_mem_gen_v8_0" as protected.

Has anyone else seen this error before? I cannot find anything about it. I have already tried recompiling the libraries and that did not work.

Thank you!

 

[TrickyDicky]

Sounds like you have some encrypted code. You may only be able to compile it in vivado