ganesh018
Newbie level 3
i am doing a project on generation of true random numbers in FPGA, and my program was running fine with no errors in Modelsim but when i loaded the same in xilinx the below error is shown. but the problem is there is no line 62.
"F:/M-TECH/s4/finals/all latest working/topp/topp/ring1.vhd" Line 62. parse error, unexpected $, expecting END
"F:/M-TECH/s4/finals/all latest working/topp/topp/ring1.vhd" Line 62. parse error, unexpected $, expecting END