error in xilinx ise. pls help my project final is this week

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ganesh018

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i am doing a project on generation of true random numbers in FPGA, and my program was running fine with no errors in Modelsim but when i loaded the same in xilinx the below error is shown. but the problem is there is no line 62.

"F:/M-TECH/s4/finals/all latest working/topp/topp/ring1.vhd" Line 62. parse error, unexpected $, expecting END
 

Is this a syntax error??
 

he's claiming its an error that isn't in the file.

My suggestion is to confirm that the file is the correct file. eg, that there isn't a different file that you've been modifying.

I didn't think ISE had the issue with concatenating files, but maybe it does. A long time ago and in verilog, I would have issues where not placing an "endmodule" at the end of a file would cause an error most of the time, but it would be shown as a syntax error on the next file.
 

Re: error in xilinx ise. pls help my project final is this w

thanks for the help it worked.
 

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