Error in Multiplication of 8 bit ALU VHDL code

[graciousparul]

Following code simulates and shows the testbench perfectly for all the cases except multiplication ,
Can anyone help me out ?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity alu is
port
(a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
c: in std_logic_vector(2 downto 0);
y: out std_logic_vector(4 downto 0));
end alu;

architecture Behavioral of alu is

begin
process(c)

variable X:std_logic_vector(4 downto 0);
begin
case c is
when "000"=>y<=("0" & a)+("0" & b);
when "001"=>y<=("0" & a)-("0" & b);
when "010"=>y<=("0" & a)*("0" & b);
when "011"=>y<=("0" & a) or ("0" & b);
when "100"=>y<=("0" & a) and ("0" & b);
when "101"=>y<= not ("0" & b);
when "110"=>y<=("0" & a) xor ("0" & b);
when "111"=>y<=("0" & a) nand ("0" & b);
when others=>null;
end case;
end process;


end Behavioral;


I am unable to get the ouptut for multiplications .