#### mostafa ahmed

##### Member level 1

I'm a beginner in VHDL language. I already tried to write a simple code for complex number a matrix. But the problem I found a strange error. I tried to search for this error but I didn't find exact solution.

My program is

PHP:

```
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:26:17 01/14/2013
-- Design Name:
-- Module Name: code_ver1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_complex.all;
use IEEE.math_real.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity code_ver1 is
Port ( e : in STD_LOGIC;
clk : in STD_LOGIC;
c : out STD_LOGIC);
end code_ver1;
architecture Behavioral of code_ver1 is
Type matrix Is Array (0 To 7) OF complex;
signal v_matrix : matrix;
Type pulses Is Array (0 To 7, 0 To 5) OF std_logic;
constant pulses_matrix : pulses:=(('0','0','0','1','1','1'),('1','0','0','0','1','1'),('1','1','0','0','0','1'),('0','1','0','1','0','1'),('0','1','1','1','0','0'),('0','0','1','1','1','0'),('1','0','1','0','1','0'),('1','0','0','1','0','0'));
-- signal a, b : complex :=(0.0,0.0);
begin
process (clk)
begin
v_matrix(0)<=(0.0,0.0); -- v0 = 0;
v_matrix(1)<=(133.3333,0.0); -- v1 = 2/3*Vdc
v_matrix(2)<=(66.666667,115.470054); -- v2 = 1/3*Vdc + 1j*sqrt(3)/3*Vdc
v_matrix(3)<=(-66.66667,115.470054); -- v3 = -1/3*Vdc + 1j*sqrt(3)/3*Vdc;
v_matrix(4)<=(-133.3333,0.0); -- v4 = -2/3*Vdc;
v_matrix(5)<=(-66.66667,-115.470054); -- v5 = -1/3*Vdc - 1j*sqrt(3)/3*Vdc;
v_matrix(6)<=(66.666667,-115.470054); -- v6 = 1/3*Vdc - 1j*sqrt(3)/3*Vdc;
v_matrix(7)<=(0.0,0.0); -- v7 = 0;
end process;
end Behavioral;
```

and the error is

=======================================================================

* HDL Analysis *

=========================================================================

Analyzing Entity <code_ver1> in library <work> (Architecture <behavioral>).

INTERNAL_ERROR:Xst:cmain.c:3464:1.56 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support.

Process "Synthesize - XST" failed

Can anyone help me please. I will appreciate your help.

Thanks in avance.

Mostafa