Encrypted verilog usage in Xilinx ISE ??

[anilineda]

Hello,


we work on cadence tools and we have knowledge on how to perform encryption/decription and IP protection using NCPROTECT . but what is the standard encryption method so that the customer can use it on their EDA tools particularly Xilinx ISE.

cadence says -ip200x option is the standard IEEE encryption ,I used it and got a "design.vp" file. but ise wont recognise it at all.

some one please help me
regards,
Anil

 

[dpaul]

If encryption types do not match then it is a problem.

You need to encrypt the RTL using Xilinx encryption (whatever it uses).

These links would also help you:
http://forums.xilinx.com/t5/Design-Tools-Others/IP-encryption-and-Decryption/td-p/414859
http://forums.xilinx.com/t5/Design-Entry/How-can-I-encrypt-RTL-source-file/td-p/318337

Not very sure but you can open up the RTL you have encrypted with Cadence and then look at the encryption headers to see Xilinx keys are included or not.

 

[anilineda]

Not very sure but you can open up the RTL you have encrypted with Cadence and then look at the encryption headers to see Xilinx keys are included or not.

how this xilinx keys looks like , i am showing a counter design before and after encryption.

module counter(clk,rst,q);
input clk;
input rst;
output reg [31:0] q;
`pragma protect
`pragma protect begin
always@(posedge clk)
begin
  if(rst)
    q <= 32'd0;
  else
    q <= q+1'b1;
end
`pragma protect end
endmodule

module counter(clk,rst,q);
input clk;
input rst;
output reg [31:0] q;
//pragma protect begin_protected
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=CDS_KEY
//pragma protect key_method=RC5
//pragma protect key_block
hGJxaalH7hN9y20bu9Q4IRaSX/DuCHAXKI6vsiWhG/74iVUXfRiDEKD0lVN79VXE
/1nYNq5yAWqCNUvG+OkZAFQIuGljVfVInICc5ujkrfYzYSF1r6AxNXQ1uQlwHvtV
AYHnNOCSWm931r1BRlMfjb5/MiAr9ef+gGeed8YyfKfdaJETXB+gpA==
//pragma protect end_key_block
//pragma protect digest_block
jnFAoxfkTkdeqOuPRcAbzhBLSeg=
//pragma protect end_digest_block
//pragma protect data_block
mlG2/ZxkpmypBQ0Wz9BvlvIheYvNmngZf87vx3u+oiW0Aa6HkjbD4nSDFv82VKuF
RCsYS9AQ/gdazXoBokgqWGbwC72e2uM5ZcuhZ8Q9MAviCGxOQlzWwI0hIMjif2IP
vsCqzKvgbeyboousISYNtWfPnyVT4SshNm31E6ot2nHxyiVzCZlC/aK21trhUQrX
LG5dMOlKCp6LQPN+AW9PLuRDHRCtvAKg0xTMRWS9RvW9WjaU02ycJjEX4sgc/rNO
Fn/Zn6/WB8uhjxcdnLICIwrQFaivLxpLIOnGuIr/nIowYDCv6FOj6bx3j5ScPFW/
uAoreTx/PNKVYkBBtszGL/WvXj/iLPXTcbWYErp7O9xhrT9ZIlr00fsbnCShCtJc
z8dwqCgF/ev3qELknfxqK9mS+8u80dd0aa0thPBRTQCfU+U5Lrj6eiZkxK8nbIlT

//pragma protect end_data_block
//pragma protect digest_block
4bO9w1rRHRTBcIyLXAM3/NHyfnI=
//pragma protect end_digest_block
//pragma protect end_protected
endmodule