Oct 25, 2004 #1 Y ymli Member level 2 Joined May 10, 2001 Messages 45 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 313 emi problems Hi, Is there any guidance to avoid EMC/EMI/EFT problem in logic level, ex: when developping the RTL verilog code. Thanks
emi problems Hi, Is there any guidance to avoid EMC/EMI/EFT problem in logic level, ex: when developping the RTL verilog code. Thanks
Oct 25, 2004 #2 E eda_wiz Advanced Member level 2 Joined Nov 7, 2001 Messages 653 Helped 58 Reputation 116 Reaction score 29 Trophy points 1,308 Activity points 6,195 eft emc EMC\EMI problems appear in the board level or in the layout level of RFICs . and can prevented only in that level .SO As far as i know There are no verilog Coding guidelines for avoiding EMC.
eft emc EMC\EMI problems appear in the board level or in the layout level of RFICs . and can prevented only in that level .SO As far as i know There are no verilog Coding guidelines for avoiding EMC.