EMC/EMI/EFT issues in logic level

[ymli]

emi problems

Hi,

Is there any guidance to avoid EMC/EMI/EFT problem in logic level, ex:
when developping the RTL verilog code.

Thanks

 

[eda_wiz]

eft emc

EMC\EMI problems appear in the board level or in the layout level of RFICs . and can prevented only in that level .SO As far as i know There are no verilog Coding guidelines for avoiding EMC.