nervecell_23
Member level 1
Hello guys,
I want to instantiate a 250:1 MUX and connect a 250bits bit vector to the input of the MUX in Verilog.
The instantiation statement would be like:
my_mux u(
.input1 (in[0]),
.input2 (in[1]),
.input3 (in[2]),
....
.input250 (in[249])
);
The question is instead of manually connect each port and repeat 250 times like the statements above, is there any efficient way to construct the connection?
It is possible to use generate for loop to instantiate multiple modules in a smart way, do we have any similar technique for my case? Any suggestion are appreciated!
Thanks a lot!
I want to instantiate a 250:1 MUX and connect a 250bits bit vector to the input of the MUX in Verilog.
The instantiation statement would be like:
my_mux u(
.input1 (in[0]),
.input2 (in[1]),
.input3 (in[2]),
....
.input250 (in[249])
);
The question is instead of manually connect each port and repeat 250 times like the statements above, is there any efficient way to construct the connection?
It is possible to use generate for loop to instantiate multiple modules in a smart way, do we have any similar technique for my case? Any suggestion are appreciated!
Thanks a lot!