[SOLVED] Efficient way to connect 250:1 MUX in Verilog

[nervecell_23]

Hello guys,

I want to instantiate a 250:1 MUX and connect a 250bits bit vector to the input of the MUX in Verilog.
The instantiation statement would be like:

my_mux u(
.input1 (in[0]),
.input2 (in[1]),
.input3 (in[2]),
....
.input250 (in[249])
);

The question is instead of manually connect each port and repeat 250 times like the statements above, is there any efficient way to construct the connection?

It is possible to use generate for loop to instantiate multiple modules in a smart way, do we have any similar technique for my case? Any suggestion are appreciated!

Thanks a lot!

 

[FvM]

Instead of instantiating a multiplexer module, a single line of behavioral code can perform the intended function.

But if you need to connect a module with 250 inputs, then they have to be connected explicitely.

 

[nervecell_23]

Thanks FvM,
statement like assign out=(sel)?in1:in2 would construct a mux but could you give further suggestion on how to describe a mux with large amount of inputs (each input is connected to a segment in a data bus )?

I tried the following code but doesn't work ('in' is a 500bits data bus and is connected to a 2bits 250:1 mux)

always@(sel or in)
	begin
	  assign out = in[2*sel+1:2*sel];
end

The error reports 'sel' is not constant.
How should i change the code to fix this?

Thanks!

 

[dave_59]

See indexed part selects in 11.5.1 Vector bit-select and part-select addressing of the 1800-2012 LRM

assign out = in[2*sel+:2];

 

[nervecell_23]

Thanks Dave.