edge triggered latch

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mohamedhany

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I designed a d flip flop using cadence. I want it to work with the rising edge of the clock (pulse wave). Any idea on how to do that?
 

In usual digital logic terminology, a latch is level triggered, in contrast to an edge triggered flip-flop.

The standard topology for edge triggered FF utilizes two latches in master-slave connection. You find it discussed in any useful digital logic text book. See below an implementation with double-throw transmission gates.

 

what is the Rn input?

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what is the Rn input. Is it reset?
 

RN = active low reset. All blocks are basic CMOS circuits. The transmission gate designators are somehow confusing, in fact is CN the active high input and C active low, clarified by the C=0 marking.
 
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