Dual Transistor Realization/Packaging

[stenzer]

Hi,

I'm curious how dual MOSFET or BJT transistors are "realized/finalized". Are the two transistors are realized on the same wafer? If yes, is each one cutted out from the wafer resulting in only single transistors or are they cut out pair wise? What is the benefit of both approaches by means of e.g.

• wafer yield
• accuracy
• handling/processing time
• accuracy/matching
• required package place
• and so on...

Are there any differences if it comes to a complementary pair like the BC846BPN [1] (NPN/PNP) or if the same transistor type is used like for the BC846BS [2] (NPN/NPN)?

On the web I couldn't find anything specific (probably I used the wrong keywords "wafer", "dual transistor", "package", etc.). From my courses (lon, long, time ago) I can remember that for trimmed pairs two transistors from the same waver are used, but I do not know how they further processed (cutting & bonding).

[1] https://assets.nexperia.com/documents/data-sheet/BC846BPN.pdf
[2] https://assets.nexperia.com/documents/data-sheet/BC846BS.pdf

I'm thankful for any explanation, and for hints for some further reading like app notes.

BR

 

[dick_freebird]

I don't think I'd generalize it. I've seen dual and
quad bipolar transistors on a single die (dielectric
isolation technology), I know RCA made some
on JI technology back in the day, ALD makes
quad FETs and so on.

But I've also seen multichip-module-style products
with the two dice physically separate.

If you find a die level datasheet these often have
a die photo and pad coordinates, which would
tell the tale (and if there is no die-level datasheet
there's a good chance it's a multi-die product
at the package level).

 

[FvM]

Datasheet specifications reveal that BC846 and many similar dual transistors are dual chip devices. They have no particular matching spec. Thermal coupling is slightly better than with separate packages.

 

[stenzer]

Hi,

Datasheet specifications reveal that BC846 and many similar dual transistors are dual chip devices.

with dual chip device two single/stand -alone transistors are meant?

Sorry but I'm not able to find any information regarding this dual chip approach within the datasheet. Please highlight the specific parameter which indicates it. Or is it somehow indicated by the thermal caracteristics?

BR

 

[FvM]

It can be seen both by the thermal resistance data and by the lack of a voltage rating between both devices.

 

[stenzer]

... by the thermal resistance data

As the thermal resistance is stated per device, and no combined value is given?
@FvM do you have a single die realization in mind, which I can have a look to compare it with the two initially linked ones?

BR

 

[FvM]

An example of monolithic transistor pair, I guess junction isolated. https://www.analog.com/media/en/technical-documentation/data-sheets/SSM2212.pdf

--- Updated Mar 12, 2021 ---

This transistor pair is designated "intrinsically matched", the datasheet explains this as using adjacent dies from a wafer. Which also implies that it's a multi-chip package.

https://www.diodes.com/assets/Datasheets/ds30436.pdf