anupam.mandlas
Newbie level 4
Hello all,
i am trying to create a dual port ram in vhdl.
this dual port ram has 2 different clock 2 wr enable one for each port.and seperate data out bus.and sepearte rd and wr add.
while i am synthesizing it in quartusII then its creating no of latches .and not able to synthesis properly..
what should i do???
thanks
Anupam
i am trying to create a dual port ram in vhdl.
this dual port ram has 2 different clock 2 wr enable one for each port.and seperate data out bus.and sepearte rd and wr add.
while i am synthesizing it in quartusII then its creating no of latches .and not able to synthesis properly..
what should i do???
thanks
Anupam