dual port ram with two clock synthesis problem ram_block creating latchs

[anupam.mandlas]

Hello all,

i am trying to create a dual port ram in vhdl.
this dual port ram has 2 different clock 2 wr enable one for each port.and seperate data out bus.and sepearte rd and wr add.


while i am synthesizing it in quartusII then its creating no of latches .and not able to synthesis properly..

what should i do???


thanks
Anupam

 

[FvM]

what should i do???

Follow the rules for RAM inference in the Quartus software manual, or even simpler, use a VHDL dual port RAM template provided by the Quartus editor. I stopped analyzing your design, when I saw, that you implemented an asynchronous read operation. It's not supported by the FPGA RAM block, so it can't be synthesized.

 

[anupam.mandlas]

Hello sir,
thanks for reply..i made this design sync.but still there are few problems..i dont want to infer the altera ram block.want to use registers.and i have to update the ram_block signal according to the two different clock.which is not possible..so is there any other solution?

or is it possible to make dual port ram using the single port ram?

 

[FvM]

i dont want to infer the altera ram block.want to use registers.and i have to update the ram_block signal according to the two different clock.which is not possible..

I fear, I don't understand your intentions any more.
You previously mentioned:

i am trying to create a dual port ram in vhdl

Which in my understanding implies using a FPGA internal RAM. If you want to model a dual port RAM with registers, you should tell. But I think, it's involving a rather complex synchronization between two clock domains. You may want to sketch the register logic on a paper to get an idea of the structure.

 

[anupam.mandlas]

yes i want to model a dual port RAM with registers....

 

[FvM]

Thanks for the clarification. I would be easy when writing only from one side. But a true dual-port RAM requires special transistor level logic, that can't be synthesized with regular FPGA LEs.