HighTechEE
Newbie level 3
Hello All,
Anyone have experience/a favorite EDA tool to take DSP algorithms into FPGA design flow? My design flow will be Matlab modeling to generate the algorithms then would like to generate a synthesizable HDL code (preferably VHDL) as a result.
The options appear to be:
1. Handcrank out the VHDL brute force, con - difficult/time consuming.
2. Generate 'C' code via the algorithms, then run that through a tool to generate VHDL, con - C code doesn't lend to concurrency & pipelining very well.
3. Use a 3rd party tool that would take Matlab .m code and go straight to HDL for synthesis, con - may not exist!...
Thanks in advance for your responses,
HighTechEE
Anyone have experience/a favorite EDA tool to take DSP algorithms into FPGA design flow? My design flow will be Matlab modeling to generate the algorithms then would like to generate a synthesizable HDL code (preferably VHDL) as a result.
The options appear to be:
1. Handcrank out the VHDL brute force, con - difficult/time consuming.
2. Generate 'C' code via the algorithms, then run that through a tool to generate VHDL, con - C code doesn't lend to concurrency & pipelining very well.
3. Use a 3rd party tool that would take Matlab .m code and go straight to HDL for synthesis, con - may not exist!...
Thanks in advance for your responses,
HighTechEE