DSP algorithms to FPGA design flow...

[HighTechEE]

Hello All,

Anyone have experience/a favorite EDA tool to take DSP algorithms into FPGA design flow? My design flow will be Matlab modeling to generate the algorithms then would like to generate a synthesizable HDL code (preferably VHDL) as a result.

The options appear to be:
1. Handcrank out the VHDL brute force, con - difficult/time consuming.
2. Generate 'C' code via the algorithms, then run that through a tool to generate VHDL, con - C code doesn't lend to concurrency & pipelining very well.
3. Use a 3rd party tool that would take Matlab .m code and go straight to HDL for synthesis, con - may not exist!...

Thanks in advance for your responses,
HighTechEE

 

[eltonjohn]

One flow of FPGA design of DSP block is to use a MATLAB COMPILER capable of generating SYTHETIZABLE VHDL code . like ACCELFPGA .But because not all MATLAB functions are external and matlab code is avalaible you have to buy some LIBRARIES .. and this product being not very old .. a lot of functions are missing ,...But the typical DSP functions are well present .. This to me is the BEST way to design DSP blocks from MATLAB and SIMULINK .. Now there is a nes enviroment called symplicity DSP . I havent played with it yet . I'm in the process of installing it for evaluation ..

 

[ahmadagha23]

Hi where can I find evaluation version of symplicityDSP?

 

[ljkong]

maybe you can write your algorithms using C code. then you can use Catapult C synthesis from Mentor to transfer c to hdl.
this is the other solution.
i have posted the introduce of this tool.
you can search it.

 

[dewdrop]

If you are using Altera's FPGA, you can use the
DSP Builder, which can transform the Matlab design
into RTL.