Greatrebel
Member level 3
Hi all,
I am designing P&R for a digital chip. After trial routing, I got thousands of DRC violations, most of which are M1 to M1 violations and happen in standard cells. The thing is that after trial routing, Via between M1 and M2 are generated. Those Vias have a small portion of M1 which break the spacing design rule to other M1 wire in standard cells. It seems like the orientation of Via M1 causes some violations. They are all horizontal.
Can anyone tell me how to fix those violations which are still there after Nanorouting. and how to change the orientation of Via.
Thanks in advance
I am designing P&R for a digital chip. After trial routing, I got thousands of DRC violations, most of which are M1 to M1 violations and happen in standard cells. The thing is that after trial routing, Via between M1 and M2 are generated. Those Vias have a small portion of M1 which break the spacing design rule to other M1 wire in standard cells. It seems like the orientation of Via M1 causes some violations. They are all horizontal.
Can anyone tell me how to fix those violations which are still there after Nanorouting. and how to change the orientation of Via.
Thanks in advance