DRC violation after trial routing

[Greatrebel]

Hi all,

I am designing P&R for a digital chip. After trial routing, I got thousands of DRC violations, most of which are M1 to M1 violations and happen in standard cells. The thing is that after trial routing, Via between M1 and M2 are generated. Those Vias have a small portion of M1 which break the spacing design rule to other M1 wire in standard cells. It seems like the orientation of Via M1 causes some violations. They are all horizontal.

Can anyone tell me how to fix those violations which are still there after Nanorouting. and how to change the orientation of Via.

Thanks in advance

 

[dionieco]

Hi
How many layers for route do you have?
Don't use M1 for trial route!!
M1 is used for cells.

The orientation of via is defined in LEF file, i supose!

 

[Greatrebel]

Hi dionieco,

thank you for your reply. I use M2 to M9 for routing. But the M1 in Via of M1 to M2 can not be avoid. If orientation of Via is defined in LEF, does it mean that I can not change it?

 

[skyismylimit]

There is a command in both ICC and nanoroute to make sure that the via1 falls completly within the M1 pin of the std cell.. This is one of steps that would help in improving the DFM (LCC)..

 

[kumar_eee]

Your LEF should have all the possible combination of VIA definition like M1 & M2 Horizontal, M1 Horizontal & M2 Vertical, & etc.

Please check your lef & may be you would want modify the same locally.

 

[Greatrebel]

to skyismylimit:

I used the following commands for via optimization

setNanoRouteMode -quiet -drouteUseMultiCutViaEffort high
setNanoRouteMode -quiet -drouteMinimizeViaCount true
setNanoRouteMode -quiet -droutePostRouteSwapVia multiCut

routeDesign -viaOpt

But the problem is still there, and the number of violations increased after nanoroute

to kumar_eee:

I found some via defination in LEF

VIA VIA12_1cut DEFAULT
RESISTANCE 1.2000000000 ;
LAYER M1 ;
RECT -0.115 -0.070 0.115 0.070 ;
LAYER VIA1 ;
RECT -0.065 -0.065 0.065 0.065 ;
LAYER M2 ;
RECT -0.070 -0.115 0.070 0.115 ;
END VIA12_1cut

VIA VIA12_1cut_H DEFAULT
RESISTANCE 1.2000000000 ;
LAYER M1 ;
RECT -0.115 -0.070 0.115 0.070 ;
LAYER VIA1 ;
RECT -0.065 -0.065 0.065 0.065 ;
LAYER M2 ;
RECT -0.115 -0.070 0.115 0.070 ;
END VIA12_1cut_H

VIA VIA12_1cut_V DEFAULT
RESISTANCE 1.2000000000 ;
LAYER M1 ;
RECT -0.070 -0.115 0.070 0.115 ;
LAYER VIA1 ;
RECT -0.065 -0.065 0.065 0.065 ;
LAYER M2 ;
RECT -0.070 -0.115 0.070 0.115 ;
END VIA12_1cut_V

Obviously, there are both vertical and horizontal options, but I do not know why the router of Encounter choose the one breaking design rules instead of the correct one. Do you know which command can be used to make Encounter optimize it.

Thank for both of you

 

[shelby]

Can you meet the VIA spacing rules with those VIAs? What is your VIA spacing, Metal1 spacing and Metal1 min width?

 

[dionieco]

You can Change the LEF file.
Make a copy and change the file.

 

[Greatrebel]

I do not have any design rule documentations at hand. From the layout, it seems like Via spacing is ok, the problem is the M1 space.

To dionieco,

How can I let Encounter choose the right Via macro instead of changing the lef, because I prefre to keep using the default lef.


Thank you very much

 

[dionieco]

to Greatrebel

I don't know....sorry!!!

 

[kumar_eee]

@Greatrebel,
I got to see your query on cadence forum & found the following answer from someone.

Trial routing is dirty routing that typically used for estimation. So, DRC violations are expected. But if they still exist after Nanorouting (I mean the same violations) you need to check that dirty routing is deleted by NanoRoute before performing actual global/detail phase. Use editDelete -type Signal to delete all signal wires before NanoRoute. Please notice that clock wires will be deleted too. You can deselect it from deletion by using editSelect/editDeselect commands.

Finally we've got the answer.