doubt in fault simulation process

[cnuvasu86]

Hi All,

I have one basic doubt in fault simulation. During pattern generation for manufacturing faults the ATPG tool will do fault simulation(say parallel fault simulation), in that case will it really modify netlist to insert fault or how this will do?

~Srini

 

[ConradATPG]

Every ATPG has to fault simulate the vectors they generate or they would
never complete test generation for any design.

They don't modify your netlist file. They work on their own binary internal
representation of the netlist in memory.

 

[ljxpjpjljx]

yes,otherwise your netlist can't be stable!

 

[avinashch]

netlist is your design so modifying a netlist means modifying ur design as well. i dont think a test generation tool modifies your netlist. your faults are detected on the basis of various test algorithms.