doubt in digitaldesign(morrismano) setup time description

[vlsi_maniac]

hi,this is regarding edge triggered ff setup time described in morris mano.
it says that D input must be maintained constant prior to the application of pulse and if it changes with pulse at zero the output of nand gates (1 & 4) changes.
but what is the issue with the statement - though the output changes the outputs at nand gates (2 & 3) are at 1 only.
so how does it conclude setup time violation.

i have uploaded images.
please clear my doubt.

 

[always84]

Re: doubt in digitaldesign(morrismano) setup time descriptio

You can use tools like synopsys Design Compiler, and constrainting your design to respect the setput time, it optmize also area and hold time, and if there is violation of contraints (constraits depending on tecnology in use) you can use tecnics like floorplaning and so on.. in this way is the tool that tries to respect the constraints putting pipeline states and so on..

 

[bulx]

Re: doubt in digitaldesign(morrismano) setup time descriptio

Assume your cuircuit was in state shown in first picture, and then both CP and D went high simultaneously. If you draw out what happens labouriously, you'll find that R and S will not settle to a fixed vlaue, they'll keep toggling. See picture. Every line corresponds to the output of the gates after one gate delay.



In a real circuit, they will settle to some indeterminate value.

However, if D had been given after the rising edge of CP, this would not happen.
- b