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Mentor offers two different levels of Systemverilog support.
For Modelsim PE/LE/SE, the Verilog-license gives you Verilog and Systemverilog(Design) support. Systemverilog(Design) means language constructs for synthesizeable-RTL.
To get COMPLETE systemverilog support (design, assertion, testbench), Mentor offers the Questasim option for Modelsim/SE. This Questasim is a SEPARATE license, and adds assertion/testbench features.
Cadence's Incisive is similar. I think the basic Incisive HDL simulator only offers basic Systemverilog support. To get Systemverilog-assertions/testbench features, you must upgrade to the Cadence 'Team Design Simulator' (or Elite Simulator).