digital PLL frequency using fpga

[jadedfox]

digital pll fpga

In a design of digital -pll using fpga, what is the frequency achieved for operation??

 

[FvM]

fpga implementation of digital pll

What kind of PLL are you intending? Most FPGAs have dedicated PLLs for clock synthesis. These are analog PLLs generating a pure, low jitter clock, up to 0.5 or 1 GHz usually. An ADPLL (all digital PLL) is a discrete time clock sampled by the system clock, mainly constrained by the logic and register speed and the acceptable jitter for the generated clock. Sample frequencies up to several 100 MHz are possible with today's FPGA.

 

[jadedfox]

pll fpga

i'm trying to implement ADPLL in an FPGA..
what lock range can be achieved by fpga implementation