Sorry I thought I had uploaded the correction. Attached is the correct schematic. I don't know why the site does not allow me to edit and clean up the post.your schematic is incorrect
co is the carry out and should go to the carry in
s1 is an output, and should go with s0,s2 and s3
Hi,one of the counters with a 1 khz com signals and the second counter with 512 hz signals.
Hi:Hi,
Your schematichs show both counters with the same input. Not independent 1kHz / 512Hz.
Both counters should ideally be
* 1kHz --> 31 (31.25)
* 512 Hz --> 16
Both have an uncertainty of +/-1
How do you simulate / test it?
Try a simulation software and show us the results
Klaus
I wonder if your answer is based on the details of my post or are you responding to the title of my post?Hi,
Some CIN and CO are unconnected. Never leave inputs unconnected.
To capture a state you may use a latch or a DFF.
Or use a logic analyzer.
Klaus
I do not simulate. I have hardware circuit on breadboard and I need someone with practical experience to tell me how can I capture the sum at outputs of the adders.
... Also, in order to feed well formed signals to the counters, I take the signals from a 4040 divider that is used with a 32khz time base generator.
I will try that. Thank you for your reply.test to see if the counters and adders are working correctly by slowing down the clocks enough that you can measure each of the 8
counter outputs and each of the adder outputs before the next clock and the data changes.
OR remove the clock to the two counters and replace with a switch so you can pulse one counter,
measure all the counter and adder outputs to see if the circuit works properly
do this at several different values for both counters.
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