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Digital Counters Counts Sample External Frequency Wrongly

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Khazan

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Please see the attached schematic. I am experimenting with a circuit for sampling an external frequency. At first, I suspected the breadboard and I replaced it with no success and then l I realized that the counters do not always count correctly.

I would like to know if anybody understands what mistake I have in my circuit which results in wrong count. It seems to me the only reason could be timing. I also experimented with timbases of 8, 16, 64, 128, 256 and 512 HZ. But it looks like that a timebase with lower frequency produces less sever errors for counting the pulses.

The update pulse (UPD) and reset pulse (RST) are derived from AND gates and inverters fed by the outputs Qk, Qj and Qi of a 4040 counter which divides a 32768 HZ frequency obtained from a crystal controlled timebase. All ICs are bypassed by a capacitor from their VCC to ground.

The 163 counters count during half cycle of the 32 HZ timebase or during 1/64 seconds. The output of the counters is fed to a 373 latch. If, for example, the counter counts the 1 HZ during 1/64 sec, then the output of the latch should be 1000 / 64 = 15.6 as either 15 or 16.

The problem is that the count, which I verify by an oscilloscope at the output of the latch, is not correct and the problem could be metastability which was not resolved with two D flip-flops is series.

Here are some examples:

Clock = I HZ, output of the latch is 00011111 which is double of 00001000.

Clock = 2 KHZ, output is 00111111 which corresponds to 4 KHZ.

Clock = 2.4 KHZ, output is 00100111 which corresponds to 2.96 KHZ.

Clock = 3 KHZ, output is 00101111 which corresponds to 3.008 KHZ and is acceptable.

Clock = 4 KHZ, output is 00111111 which corresponds to 4.032 KHZ .

Clock = 4.6 KHZ, output is 01001010 which corresponds to 4.736 KHZ .

Clock = 5 KHZ, output is 01001111 which corresponds to 5.056 KHZ .

Clock = 8 KHZ, output is 01111111 which corresponds to 8.128 KHZ .

Clock = 9 KHZ, output is 10001111 which corresponds to 9.344 KHZ .

Clock = 10 KHZ, output is 10011010 which corresponds to 9.856 KHZ .

I am particularly concerned with when the error at the output of latch is more than 65 HZ.

I use pulse generator of my oscilloscope for generating the input clock frequency to the 163 counters.

When I use output of Qf (1 KHZ) of the 4040 of the timebase generator as input clock formthe 163 counters, I do get the correct count at the output of the latch. This reveals the timing issue for getting the right count of an external frequency. So, how can we correctly read (sample) an external clock frequency that comes from a source other than the 4040?

The actual connection of counters and latch is as shown in the original schematics. I included the timebase generator, the gates, part numbers, and a picture of the oscilloscope. I had taken the pictures when I was testing 16 HZ timebase with similar results. I had two probes but unfortunately one of my probes is now defective so I could not show the pulses on one screen when I took the new picture with 32 HZ. I hope this can help. When I used a low pass filter of 100 KHZ all outputs of the latch went high. So I eliminated the filter from the circuit.

Could someone who is well experienced with digital frequency sampling and metastability tell me why the count is wrong specially when the count is double?

I appreciate your response and thank you.
 

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KlausST

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Hi,

Just to be sure:
this is no breadboard circuit?
You have a proper PCB layout with proper GND plane and a decoupling capacitor at every VCC of every IC?

Klaus
--- Updated ---

Hi,

If input is 32768 Hz then:
* A = 16384 Hz
* B = 8192 Hz
* C = 4096 Hz
* D = 2048 Hz
* E = 1024 Hz
* F = 512 Hz
* G = 256 Hz
* H = 128 Hz
* I = 64 Hz (you write 32 Hz)
* J = 32 Hz (you write 64 Hz)
* K = 16 Hz (you write 128 Hz)

I don't know how you come to your frequencies. My table above is simple...and you have a scope to simply verify it ...
(Verify your values and also verify my values ... there's always a chance that I'm mistaken)

And a breadboard is not suitable. Whether it is useful or not does not depend on the used XTAL frequency it depends on the switching speed (dV/dt) of the used ICs. You find this value maybe as "tr" and "tf" in the according datasheets.
"Not useful" does not mean that there is no chance for it to work. It is just unreliable, like: bend a wire to the left and it works, bend it to the right and it makes nonsense.

Klaus
 
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BradtheRad

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Your second counter (most significant nibble) only increments when it receives a carry from the first counter (least significant).

Questions:

* Is the first counter enabled at every instant that it overflows? Is it disabled at any instant when it ought to overflow? So it can send a carry when it ought to?

* Likewise is the second counter enabled at every instant it ought to receive a carry?

Your binary outputs have sequences of several 0's and several 1's. It's more orderly than we would expect.
--- Updated ---

And, are you counting in binary? Or in BCD (binary coded decimal)?
 
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KlausST

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You use:
Outputs K | J | I for timing control.
According my table this results in a repeat frequency of 16 Hz or in time: 1/16s = 62.5 ms.
Just focusing on those 3 outputs:
K | J | I
0 0 0 count
0 0 1 upd
0 1 0 rst
0 1 1 count
1 0 0 count
1 0 1 count
1 1 0 count
1 1 1 count
So you count 6/8 of the time. 6/8 of 62.5ms = 46.875ms
(Please verify my results with your scope)

Other issues:
* your low_nibble_counter goes to high bits of '373 and vice versa
* where does "tb" come from?

Klaus
 

Khazan

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You use:
Outputs K | J | I for timing control.
According my table this results in a repeat frequency of 16 Hz or in time: 1/16s = 62.5 ms.
Just focusing on those 3 outputs:
K | J | I
0 0 0 count
0 0 1 upd
0 1 0 rst
0 1 1 count
1 0 0 count
1 0 1 count
1 1 0 count
1 1 1 count
So you count 6/8 of the time. 6/8 of 62.5ms = 46.875ms
(Please verify my results with your scope)

Other issues:
* your low_nibble_counter goes to high bits of '373 and vice versa
* where does "tb" come from?

Sorry for the misprint which created confusion about the frequencies and thank you for pointing at the mistake. In fact, the Qi = 128 Hz, Qj = 64 Hz and Qk = 32 Hz. So your table of frequencies needs correction too.
  • 1- This is a new breadboard, so no PCB board.
  • 2- I have to get the right results on breadboard before committing to PCB board. As I mentioned in the description of the problem, “When I use output of Qf (1 KHZ) of the 4040 of the timebase generator as input clock from the 163 counters and the same two AND gates and inverters to generate the update and reset pulses, I do get the correct count at the output of the latch.” In fact I do get correct output from counters even without a latch.
  • 3- If I was counting 6/8 of the time, then I would not get the perfect count which I mentioned in the paragraph 2 above.
--- Updated ---

Your second counter (most significant nibble) only increments when it receives a carry from the first counter (least significant).

Questions:

* Is the first counter enabled at every instant that it overflows? Is it disabled at any instant when it ought to overflow? So it can send a carry when it ought to?

* Likewise is the second counter enabled at every instant it ought to receive a carry?

Your binary outputs have sequences of several 0's and several 1's. It's more orderly than we would expect.
--- Updated ---

And, are you counting in binary? Or in BCD (binary coded decimal)?
  • 1- Both counters are enabled to count while the TB is at logic high, and both counters are at rest while the TB is at logic low when the update and reset pulses are generated.
  • 2- The counters count in binary and their orderly output is what they produce.
 

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BradtheRad

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their orderly output is what they produce.

That is what's suspicious. I don't think we expect your first nibble counter to produce 4 ones all in a row, in the majority of cases. It's as though the count reached maximum but didn't wrap back to zero.

However the count did continue into the second nibble counter.
What do you calculate to be expected readouts for your list given in the OP: 2, 3, 4, 5, 6, 7, 8, 9, 10 kHz?
 

KlausST

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Hi,
1- This is a new breadboard, so no PCB board.
New or old...it is not suitable for fast rising/falling digital signals.

2- I have to get the right results on breadboard before committing to PCB board
Makes no sense. In this case a simulation would give more reliable results

I do get the correct count at the output of the latch.” In fact I do get correct output from counters even without a latch.
How can you verify them when they continously count / idle / reset?
3- If I was counting 6/8 of the time, then I would not get the perfect count which I mentioned in the paragraph 2 above.
Now with the new information about tb you count 50% of time and the table looks like:
Just focusing on those 3 outputs:
K | J | I
0 0 0 idle
0 0 1 upd
0 1 0 rst
0 1 1 idle
1 0 0 count
1 0 1 count
1 1 0 count
1 1 1 count
So you count 4/8 of the time. 4/8 of 62.5ms = 31.25ms

Now the output for 1kHz and 2kHz is like expected
The output above 2kHz still makes no sense.

Maybe the breadboard, maybe a logic level problem, maybe a powersupply decoupling problem...

Show a photo of your whole circuit.

Klaus
 

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