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# Wrong value on digital counter output

#### Gigillo74

##### Member level 3
Hi all,
i've built a time base board of my discrete frequency counter design.
This board, have an issue on counting..... the value is not what it should be.
With a 320Khz input signal it is showed 100 on display.
Someone can help me to troubleshoot?
Thank You.

View attachment sch.jpg

Hi,

what an effort .... Why that complicated?

Xtal Q1 usually needs capacitors to work properly. Are you sure your circuit can work this way?
Where is Q1 this circuit from? Is it from a reliable source, like a semiconductor manufacturer or university?
4060 datasheet shows a different schematic, why don´t you use it?

Can you show your math how you come to 0.32s. I don´t get it.

With a 320Khz input signal it is showed 100 on display.
What display value do you expect?

Klaus

Hi Klaus,

Can you show your math how you come to 0.32s. I don´t get it.
So, Q1 is 10.240Mhz and with this value you can use binary div factor on divider; First div is by 16384 and you obtain 625Hz; Second and third stage div by 100 so you have 6,25Hz. Last stage div by 2 and you have 3,125Hz that is 0,32sec. In this time, only on positive clock the count will be performed so the count is made in 0,16Sec.
For example, if you have a 10khz input signal, in 0,1Sec time you can count 1000 clock cycle. In 0,16Sec you count 1600 cycle.
If you div this value by 16 (is the total div factor of the divider) you have 100 clock cycle to send to counter that will display 100.

4060 works fine.
Sorry for mistake. this is right sch.

View attachment sch2.jpg

10,240,000 / 16,384 = 625 Hz / 100 = 6.25 Hz / 2 = 3.125 Hz Gate

Your gate of 3,125 Hz opens up for 1/2 its period, or effectively
6.25 Hz.

So counter clock is (320,000 / 2) / 3.125 = 51,200

Count then divided by 4 then 8 so count = 51,200 / 32 = 1,600

So to Klaus's point how do you get 100 ?

Curious, what is the range of freqs you want to measure ?

Regards, Dana.

Hi,

we don´t know what SV6 and SV7 settings you use.

Again: what value do you expect?

Klaus

10,240,000 / 16,384 = 625 Hz / 100 = 6.25 Hz / 2 = 3.125 Hz Gate

Your gate of 3,125 Hz opens up for 1/2 its period, or effectively
6.25 Hz.
No, it is not the same. The Frequency will be 3.125 and a part of his (positive clock pulse) is the gate aperture time (0,16sec).
If you indicate 6.25Hz, positive clock pulse is 0,08Sec.
So counter clock is (320,000 / 2) / 3.125 = 51,200
It is not counter main clock. Then 320000 is input sample frequency
Count then divided by 4 then 8 so count = 51,200 / 32 = 1,600

So to Klaus's point how do you get 100 ?

Curious, what is the range of freqs you want to measure ?
The range is from some kilohertz to max 74F74 input freq.. (maybe 200mhz)
If you need more, you can apply a prescaler. A simple div by 10 let you reach 2000Mhz.
Regards, Dana.

Hi,

we don´t know what SV6 and SV7 settings you use.

Again: what value do you expect?

Klaus
SV7 setting joint pin 2 & 3 - SV6 setting joint pin 1 & 2

with input sample of 320khz, i'll expect 3200 on display

This is value on display with 320khz input sample freq.

Just as a future consideration this is a single chip approach, although limited to 32 or 24 bit counter speed
of ~ 25 Mhz and the comparator is only good for ~ 110 nS. But food for thought,. This only used ~ 15% of total
chip resources, see right hand window.

board to work with ~ $15, IDE and compiler free. Regards, Dana. Hi, in short: REF_Clk = 10,240,000 Hz --> divided by 16384 = 625Hz --> divided by 10 = 62.5Hz --> divided by 10 = 6.25 Hz --> divided by 2 = 3.125Hz --> gate_time = 1/3.125Hz * 50% duty_cycle = 0.16s Input_clock = 320,000 Hz --> divided by 2 = 160,000 Hz --> divided by 2 = 80,000 Hz --> divided by 4 = 20,000 Hz Counter: 20,000 Hz x 0.16s = 3,200 (counts) I understand so far... We don´t see how the display is driven, function of LATCH and RESET. Design issues: * no GND plane (no stable reference for signals as well as power supply) * no sufficient power supply bypass capacitors (no stable power supply) * no local power supply may lead to instable VCC * driving capacitive loads (high peak power supply currents) * asynchronous ( prone to pick up glitches ... maybe also to generate those glitches .. both may lead to timing problems) * high current LED display (causing instable VCC) * C9, R6, R7 lead to VCC/2 at input of IC5A ... which is not good idea at all. * wiring single ended signals ... and additionally combined with high currents over connectors and longer traces may lead to signal integrity problems. * using standard diodes may violate absolute_input_voltage range of the ICs. * we dont see what exact types of logic families you use. Mixing different familines may lead to logic level mismatch. .. additionally some families are nout suitbale at all: (TI) CD4060 is specified for min. 3.5 MHz @ 5V, but you use more than 10MHz. * maybe more... Klaus Just as a future consideration this is a single chip approach, although limited to 32 or 24 bit counter speed of ~ 25 Mhz and the comparator is only good for ~ 110 nS. But food for thought,. This only used ~ 15% of total chip resources, see right hand window. View attachment 186252 board to work with ~$15, IDE and compiler free.

Regards, Dana.
Hi Dana, the project is not cost oriented but have didactical value also for display part that is not shown in this post. It use a multiplexing technique with all simple logic IC.
Hi,

in short:
REF_Clk = 10,240,000 Hz --> divided by 16384 = 625Hz --> divided by 10 = 62.5Hz --> divided by 10 = 6.25 Hz --> divided by 2 = 3.125Hz
--> gate_time = 1/3.125Hz * 50% duty_cycle = 0.16s

Input_clock = 320,000 Hz --> divided by 2 = 160,000 Hz --> divided by 2 = 80,000 Hz --> divided by 4 = 20,000 Hz

Counter:
20,000 Hz x 0.16s = 3,200 (counts)

I understand so far...

We don´t see how the display is driven, function of LATCH and RESET.

Design issues:
* no GND plane (no stable reference for signals as well as power supply)
* no sufficient power supply bypass capacitors (no stable power supply)
* no local power supply may lead to instable VCC
* driving capacitive loads (high peak power supply currents)
* asynchronous ( prone to pick up glitches ... maybe also to generate those glitches .. both may lead to timing problems)
* high current LED display (causing instable VCC)
* C9, R6, R7 lead to VCC/2 at input of IC5A ... which is not good idea at all.
* wiring single ended signals ... and additionally combined with high currents over connectors and longer traces may lead to signal integrity problems.
* using standard diodes may violate absolute_input_voltage range of the ICs.
* we dont see what exact types of logic families you use. Mixing different familines may lead to logic level mismatch.
.. additionally some families are nout suitbale at all: (TI) CD4060 is specified for min. 3.5 MHz @ 5V, but you use more than 10MHz.
* maybe more...

Klaus
Thank you Klaus for your time.
I'm going to verify and modify design issue you have suggested.
I'll post news after mods.
Luigi

As you can see from the image, the display now shows the correct frequency value! I managed to find the problem! It was enough to have a chat with the counters IC who told me how they was reading the wrong values and so, by inverting the outputs of the 4 counters, the problem was solved... seriously, the problem was located in the inversion of the counter outputs. I noticed this because the display digits occasionally showed a blank digit and from the datasheet of 4511 this meant that it was receiving an incorrect BCD sequence. Thank you all for the suggestions and thank you Klaus for the list of measures that I will implement on the time base board
.

"Didactical value", think of the PSOC as a workbench on a proto board with parts on it
(but actually in chip). The community did a few 74xxxx components in it in addition
to its vendor standard components. In PSOC language a component is an onchip resource.

So standard resources in it look like (multiple copies in many cases) :

And the community has added :

So with tool you wire these up internally and out to pins. In fact you can create your own components
using schematic capture and its logic elements and / or verilog. So in a sense you have a pile of parts
internal to manipulate. You can do codeless logic design and of course use the ARM processor as well.
All drag and drop....gui heaven For future reference.

Regards, Dana.

Good work.

1 suggestion

But if the CMOS has what I expect , it can tolerate the 5.9V pulse with internal ESD protection also assisting with latch-up protection.
But still best to avoid.

Last edited:

"Didactical value", think of the PSOC as a workbench on a proto board with parts on it
(but actually in chip). The community did a few 74xxxx components in it in addition
to its vendor standard components. In PSOC language a component is an onchip resource.

So standard resources in it look like (multiple copies in many cases) :

View attachment 186254

And the community has added :

View attachment 186255

So with tool you wire these up internally and out to pins. In fact you can create your own components
using schematic capture and its logic elements and / or verilog. So in a sense you have a pile of parts
internal to manipulate. You can do codeless logic design and of course use the ARM processor as well.
All drag and drop....gui heaven For future reference.

Regards, Dana.
Hi Dana, thsnk you for your PSOC suggestion.