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Digital addition

Khazan

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Hello experts:

As the attached schematic shows, I am experimenting a circuit for adding two numbers represented by two digital counters and two cascaded 4 bits adders (74hc283). I tested separately with cascaded 74hc163 and with asynchronous 74hc4040 counters and I ended up with the same questions.

I fee one of the counters (at pin 10) with a 1 khz clk signals and the second counter with 512 hz signals. All signals are well formed square signals.

I use 16hz crystal-controlled time base. The counters count during logic high of the time base that is 1/32 sec or about 31 msec. The counters are reset (at pin 11) in the second half of the logic-low of the time base.

When I verify the outputs of the first counter, my prob realizes pulses at some of the outputs and I consider them as logic high. So that the output of the first counter is binary 00011111 to represent the 1khz clk input, almost as expected. The output of the second counter is binary 00001111 to represent the 512 hz clk input also during the 1/32 sec. So far so good.

I feed input a[] of the cascaded adders by the outputs of the first counter and input b[] of the adders by outputs of the second counter. My expectation is to see the correct sum as binary number 00101110 at output s[] of the 8 bits adder, the same way that I see the correct binary numbers at the outputs of the two counters. But instead, I see binary 00111111 as the sum. If I change the clk input of the first counter to 2khz and I leave the clk input of the second counter as it was 512 hz, I see binary number 01111111 instead of the correct sum 01001110 as sum at outputs s[] of the adder. If I change the clk input of the first counter to 512khz like the second counter, I see the correct output of 00011110 as sum at outputs s[] of the adder.

Is my expectation to see the correct sum at output s[] of the adder justified while the counters are counting during the logic high of the time base?

If so, why do I get wrong sum?

If my expectation is wrong then how am I supposed to get the right sum while the counters are counting during the logic high of the time base?

Please note that it is not about what kind of counters I am using. It is about the wrong sum no matter which counter I use.

Thank you
 

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barry

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Terrible schematic; why don’t you use the correct symbols for your logic elements?

But it sounds like perhaps a timing issue. Are all your clocks synchronous? A real schematic and timing diagram might Help.
 

KlausST

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Hi

And please draw a timing diagram.
Both mainly for yourself to see what (you are trying to) do. But also for us to understand it's (desired) function.

To me the "carry" wiring looks odd.

There are two ANDs. Each has a clock input. And each has a "gating" input. You need to understand that not the gating frequency determines the counter values but it's timing.

Thus a 32 Hz (or 100Hz) gating will lead to almost the same counter output than your 16Hz gating.
But modifying the gate's duty cycle will modify the counter output.

Thus a timing diagram is that important.

Klaus
 

wwfeldman

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as is suggested above, the carry in and carry out connections appear backward
the 283 at the top should have ground at carry in and its carry out should go to the carry in or the 283 at the bottom

try stopping all of the clocks
then look at the output of the counters and the adder - see if they agree then
advance one counter, and look again
after a few tests without the clocks, it should be clear if the counters and adders are connected correctly and working
do this for a few numbers <16, a few where the lower 4 bits are all 0, and a few where both half bytes are between 1 and 15

switch to synchronous counters to produce the clock signals - 1kHz, 512Hz, 16 Hz

what is the purpose of the reset?
try turning the reset off - let the circuit run
 

Khazan

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Hello electronics experts:

I am experimenting a circuit for adding two numbers represented by two digital counters and two cascaded 4 bits adders (74hc283). I tested separately with cascaded 74hc163 and with asynchronous 74hc4040 counters and I ended up with the same results.

enter image description here

I feed one of the counters with a 1 khz com signals and the second counter with 512 hz signals. All signals are well formed square signals.

I use 16hz crystal-controlled time base. The counters count during logic high of the time base that is 1/32 sec or about 31 msec. The counters are reset in the second half of the logic-low of the time base.

When I verify the outputs of the first counter, my oscilloscope realizes pulses at some of the outputs and I consider them as logic high. So that the output of the first counter is binary 00011111 to represent the 1khz clk input, almost as expected. The output of the second counter is binary 00001111 to represent the 512 hz clk input also during the 1/32 sec. So far so good because I can read the output of the counters correctly.

I feed input a[] of the cascaded adders by the outputs of the first counter and input b[] of the adders by outputs of the second counter. I expect to see the same pulsing output pins of the adders to show correct sum. My expectation is to see the correct sum as binary number 00101110 at output s[] of the 8 bits adder, the same way that I see the correct binary numbers at the pulsing pins of the two counters. But instead, I see binary 00111111 as the sum. If I change the clk input of the first counter to 2khz and I leave the clk input of the second counter as it was 512 hz, I see binary number 01111111 instead of the correct sum 01001110 as sum at outputs s[] of the adder. If I change the clk input of the first counter to 512khz like the second counter, I see the correct output of 00011110 as sum at outputs s[] of the adder.

I understand that as the counter is cycling through the addition is performed. But my thoughts are that the total propagation delay of the counters and the adders is in the order of hundreds of nanoseconds but the counters are not counting for many milliseconds before they are reset. My expectation is to see the correct sum at output s[] of the adder at their pulsing output pins while the counters are counting during the logic high of the time base? I mean, I expect to see the right output of the adders at their pulsing output pins just like I can see the right output of the counters at their pulsing output pins. Is my expectation justified while counters periodically pause counting? If so, why do I get wrong sum?

Please note that it is not about what kind of counters I am using. It is about the wrong sum no matter which counter I use.

Your experts reply is much appreciated. Thank you
 

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wwfeldman

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your schematic is incorrect
co is the carry out and should go to the carry in
s1 is an output, and should go with s0,s2 and s3
 

Khazan

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your schematic is incorrect
co is the carry out and should go to the carry in
s1 is an output, and should go with s0,s2 and s3
Sorry I thought I had uploaded the correction. Attached is the correct schematic. I don't know why the site does not allow me to edit and clean up the post.
 

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KlausST

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one of the counters with a 1 khz com signals and the second counter with 512 hz signals.
Hi,

Your schematichs show both counters with the same input. Not independent 1kHz / 512Hz.

Both counters should ideally be
* 1kHz --> 31 (31.25)
* 512 Hz --> 16
Both have an uncertainty of +/-1

How do you simulate / test it?

Try a simulation software and show us the results

Klaus
 

wwfeldman

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remove the clocks into the counters and replace with momentary contact switches
read the outputs of the counters and the adders and see if they agree when static
 

Khazan

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Hi,

Your schematichs show both counters with the same input. Not independent 1kHz / 512Hz.

Both counters should ideally be
* 1kHz --> 31 (31.25)
* 512 Hz --> 16
Both have an uncertainty of +/-1

How do you simulate / test it?

Try a simulation software and show us the results

Klaus
Hi:

Thanks for your replay.
I do not simulate. I have hardware circuit on breadboard and I need someone with practical experience to tell me how can I capture the sum at outputs of the adders. Please se the new schematic attached to this reply. Also, in order to feed well formed signals to the counters, I take the signals from a 4040 divider that is used with a 32khz time base generator.
 

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KlausST

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Hi,

Some CIN and CO are unconnected. Never leave inputs unconnected.

To capture a state you may use a latch or a DFF.

Or use a logic analyzer.

Klaus
 

Khazan

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Hi,

Some CIN and CO are unconnected. Never leave inputs unconnected.

To capture a state you may use a latch or a DFF.

Or use a logic analyzer.

Klaus
I wonder if your answer is based on the details of my post or are you responding to the title of my post?
 

wwfeldman

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I do not simulate. I have hardware circuit on breadboard and I need someone with practical experience to tell me how can I capture the sum at outputs of the adders.
... Also, in order to feed well formed signals to the counters, I take the signals from a 4040 divider that is used with a 32khz time base generator.

test to see if the counters and adders are working correctly by slowing down the clocks enough that you can measure each of the 8
counter outputs and each of the adder outputs before the next clock and the data changes.

OR remove the clock to the two counters and replace with a switch so you can pulse one counter,
measure all the counter and adder outputs to see if the circuit works properly
do this at several different values for both counters.
 

Khazan

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test to see if the counters and adders are working correctly by slowing down the clocks enough that you can measure each of the 8
counter outputs and each of the adder outputs before the next clock and the data changes.

OR remove the clock to the two counters and replace with a switch so you can pulse one counter,
measure all the counter and adder outputs to see if the circuit works properly
do this at several different values for both counters.
I will try that. Thank you for your reply.
 

FvM

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It would make sense to show the clock generation and gating circuit. As 4040 is a ripple counter, you are likely generating glitches in the gated clock which might cause unexpeced behaviour of the driven circuit.

To allow capture of the adder result, you want a delay between gate pulse and reset.
 

KlausST

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Hi,

I recommend to be more exact in your naming the signals.
There are some issues, I'm not sure whether you want it this way or not.

Your "283" has inputs A0...A3, B0...B3 like in the datasheet
But it has S1...S4, while the datasheet says S0..S3.
Usually the number is the bit number, so input bit 0 leads to output bit 0. Not in your case.

Usually S0 is the least significant bit.

On the right bottom corner the result is totally confused.
Usually it should be in the order : D7-D6-D5-D4-D3-D2-D1-D0
(while D7 : D4 should be the outputs S3 : S0 of the higher nibble '283')
But in your case output is drawn in the order: D0-D1-D2-D3-D7-D6-D5-D4 (the right most bit (D4) is marked as 'LSB')

Klaus
 

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