This thread is driving me crazy because this is the top link when I search mmcm vs pll using the Googles.
I think this deserves a reasonable explanation. Anyone else? (I wouldn't be here if I knew the answer)
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Here's my attempt at gathering information:
Xilinx has an app note:
http://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf
Which clearly states that the differences between the mmcm and pll are... oh wait.. no, it doesn't actually say anything about the differences.
Here's a link of people that are equally confused on the Xilinx forum:
http://forums.xilinx.com/t5/7-Series-FPGAs/mmcm-differences-between-7-series-and-6-series/td-p/151028
Alright, looking back on the Xilinx app note, it points to a Xilinx user guide:
http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
Hey, here some good stuff! The mmcm in the V7 uses the same pll that the pll uses. So basically, the MMCM is just a PLL with a few extra cool features:
• Direct HPC to BUFR or BUFIO using CLKOUT[0:3]
• Inverted clock outputs (CLKOUT[0:3]B)
•CLKOUT6
•CLKOUT4_CASCADE
• Fractional divide for CLKOUT0_DIVIDE_F
• Fractional multiply for CLKFBOUT_MULT_F
• Fine phase shifting
• Dynamic phase shifting