Differences : MMCM vs PLL vs DCM

[guetguet]

Hello everyone,

I know it is possible to generate clock frequencies using a MMCM, a PLL or a DCM. Could someone tell me the difference betweem them ? Thnaks a lot

 

[mrflibble]

You can find quite a few things by doing the following two google searches:
"dcm pll difference"
"pll mmcm difference"

Those are just the evolution in clock management from DCM to PLL to MMCM in xilinx parts. For that matter, you could check the datasheets for the 6 vs 7 series xilinx devices. In the clocking resources there's tons of info on precisely this.

 

[dkmack]

This thread is driving me crazy because this is the top link when I search mmcm vs pll using the Googles.

I think this deserves a reasonable explanation. Anyone else? (I wouldn't be here if I knew the answer)

- - - Updated - - -

Here's my attempt at gathering information:

Xilinx has an app note:
http://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf

Which clearly states that the differences between the mmcm and pll are... oh wait.. no, it doesn't actually say anything about the differences.

Here's a link of people that are equally confused on the Xilinx forum:
http://forums.xilinx.com/t5/7-Series-FPGAs/mmcm-differences-between-7-series-and-6-series/td-p/151028

Alright, looking back on the Xilinx app note, it points to a Xilinx user guide:
http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

Hey, here some good stuff! The mmcm in the V7 uses the same pll that the pll uses. So basically, the MMCM is just a PLL with a few extra cool features:

• Direct HPC to BUFR or BUFIO using CLKOUT[0:3]
• Inverted clock outputs (CLKOUT[0:3]B)
•CLKOUT6
•CLKOUT4_CASCADE
• Fractional divide for CLKOUT0_DIVIDE_F
• Fractional multiply for CLKFBOUT_MULT_F
• Fine phase shifting
• Dynamic phase shifting

 

[D.A.(Tony)Stewart]

The 1st link says "The PLL is organized similar to the MMCM with exceptions noted in the Figure 1 block diagram and in the subsequent tables."
THe table shows (MMCM only)in numerous outputs.

 

[FR1985]

You can find quite a few things by doing the following two google searches:
"dcm pll difference"
"pll mmcm difference"

Those are just the evolution in clock management from DCM to PLL to MMCM in xilinx parts. For that matter, you could check the datasheets for the 6 vs 7 series xilinx devices. In the clocking resources there's tons of info on precisely this.

Hi
can you explain me the difference between MMCM and MMCM_ADV and MMCM_DRP
thank you

 

[dkmack]

Hi
can you explain me the difference between MMCM and MMCM_ADV and MMCM_DRP
thank you

Are you looking at multiple devices? I'm pretty sure the V7 only has MMCM_ADV, which I'm assuming is the advanced form of an MMCM(more features!). I've also seen DRP used as a communication bus to the core, so you can configure the MMCM after it has been programmed to an FPGA. However, these are just guesses. Can anyone verify this?

 

[mrflibble]

I haven't played with V7, but just going by the naming scheme Xilinx used on PLL modules I am guessing this is just 1 flavor MMCM. As in 1 physical item on the die, with just several different ways of accessing them. But luckily precisely for this sort of thing documentation has been invented. If you happened to find this using coregen, then there's usually a datasheet button.