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Mealy vs Moore Machine

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arminb73

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Based on this code how can I know whether it is a Mealy or a Moore machine?

1638377429205.png
 

FvM

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Mealy is characterized by output depending on input and state while with Moore, output depens only on state. What do you see?
 

barry

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You want me to do your homework for you?

There's no reason I can think of why you need to know if it's Mealy or Moore. In all my years of working with state machines, I have never, ever, given a thought to that.

Look up the definition; one of them has the output a function of both present state and inputs; the other has the output depend only on the present state.
 

dpaul

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@barry
There's no reason I can think of why you need to know if it's Mealy or Moore. In all my years of working with state machines, I have never, ever, given a thought to that.
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Neither do I, but in the university there are such exercises given to the students I guess.

The style of VHDL presented by the OP is also antiquated (clk'event and clk='1', encodings for curr_state and next_state, etc.). I has used such a SM VHDL coding style last back in 2008/2009, and it was most probably due to some limitations of the Simulation or Synthesis tool (cannot remember correctly).
 

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