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@barry There's no reason I can think of why you need to know if it's Mealy or Moore. In all my years of working with state machines, I have never, ever, given a thought to that.
Neither do I, but in the university there are such exercises given to the students I guess.
The style of VHDL presented by the OP is also antiquated (clk'event and clk='1', encodings for curr_state and next_state, etc.). I has used such a SM VHDL coding style last back in 2008/2009, and it was most probably due to some limitations of the Simulation or Synthesis tool (cannot remember correctly).