I run synopsys design compiler for a relatively large processor core and every time I get a different netlist. Is there any why to get deterministic results from this tool?
This is not true for Design compiler. I guess they implemented an stopping condition based on the time. Since the timing is dependent on the other running tasks, it become non-deterministic.
The amazing thing is how few designers really understand this behaviour. I heard a talk in a eda conference where the researcher did multiple compiles
of the same logic and saw results vary by up to 10%.
The amazing thing is how few designers really understand this behaviour. I heard a talk in a eda conference where the researcher did multiple compiles
of the same logic and saw results vary by up to 10%.